Advances in semi-conductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple cores, multiple hardware threads, and multiple logical processors present on individual integrated circuits. A processor or integrated circuit typically comprises a single physical processor die, where the processor die may include any number of cores, hardware threads, or logical processors. The ever increasing number of processing elements—cores, hardware threads, and logical processors—on integrated circuits enables more tasks to be accomplished in parallel.
In order to fully utilize the ability of computer systems to accomplish tasks in parallel, computer instructions may be reordered and scheduled prior to the execution of the instructions. However, such reordering and scheduling may result in cache coherency and processor consistency violations. Thus, the execution of reordered and scheduled code may need to be checked to ensure that such violations do not occur.